Chemical-mechanical planarization, or chemical-mechanical polishing (CMP), is a well known technique used to planarize substrates. CMP utilizes a chemical composition, known as a CMP composition (which also is referred to as a CMP slurry) for removal of material from the substrate. Polishing compositions typically are applied to a substrate by contacting the surface with a polishing pad (e.g., polishing cloth, or polishing disk) saturated with the polishing composition. The polishing of the substrate typically is further aided by the chemical activity of the polishing composition and/or the mechanical activity of an abrasive suspended in the polishing composition or incorporated into the polishing pad (e.g., fixed abrasive polishing pad).
Conventional CMP compositions and methods typically are not entirely satisfactory at planarizing substrates. In particular, CMP polishing compositions and methods can result in less than desirable polishing rates and high surface defectivity when applied to a substrate. Because the performance of many substrates is directly associated with obtaining a planar and defect free surface, it is crucial to use a CMP composition and method that results in a high polishing efficiency, selectivity, uniformity, and removal rate and leaves a high quality polish with minimal surface defects.
Polishing slurries that provide high polishing rates on silicon metal oxides and low polishing rates on polysilicon, also know as “reverse poly” or “oxide stop on poly” slurries, are desired. Such slurries are needed in the processing of various integration schemes including floating gate electrodes. The difficulty in achieving high oxide-to-polysilicon selectivity is believed to be due to the very facile removal of polysilicon in typical dielectric slurries (for example: high pH silica-based slurries).
In conventional polishing slurries containing ceria, the use of low levels (below 0.5 wt. %) of ceria can lead to local areas of overly high removal. This is demonstrated in FIG. 1 wherein, on wafer (2), features (1) represent examples of local areas of high removal and each contour line represents a 10 nm topography change into the wafer. These isolated regions of overly high removal are sometimes called “pitting”, “staining”, “spots” or “hot spots”. These spots are depressions in the surface that typically are on the order of about 0.001 to about 10 mm2 in area, and are typically about 2 to about 200 nm in depth.
Accordingly, there is a need for methods and compositions, which enable the reliable use of low solids ceria slurries for polishing silicon-containing substrates in reverse poly applications, while also providing good surface uniformity.